Analog Devices Inc. ADN4622/ADN4624 Quad LVDS 2.5 Gigabit Isolators
Analog Devices Inc. ADN4622/ADN4624 Quad LVDS 2.5 Gigabit Isolators are signal-isolated buffers that operate at up to 2.5Gbps with very low jitter. The devices integrate iCoupler® technology, enhanced for a high-speed operation to provide drop-in galvanic isolation of LVDS signal chains. AC coupling and/or level shifting to the LVDS receivers and from the LVDS drivers allows the isolation of other high-speed signals like current-mode logic (CML).
Features
- 5.7kVrms and 1.5kVrms LVDS isolators
- Complies with TIA/EIA-644-A LVDS signal levels
- Quad-channel configuration (ADN4622: 2 + 2, ADN4624: 4 + 0)
- Any data rate up to 2.5Gbps switching with low jitter
- 10Gbps total bandwidth across four channels
- 2.15ns typical propagation delay
- Typical jitter: 0.82psrms random, 40ps total peak
- Lower power 1.8V supplies
- ±8kV IEC 61000-4-2 ESD protection across an isolation barrier
- High common-mode transient immunity of 100kV/μs typical
- Safety and regulatory approvals (28-lead SOIC_W_FP package)
- UL (pending) of 5700Vrms for 1 minute per UL 1577
- CSA Component Acceptance Notice 5A (pending)
- VDE certificate of conformity (pending)
- DIN V VDE V 0884-11 (VDE V 0884-11):2017-01
- VIORM = 849VPEAK (working voltage)
- Enable or disable refresh (low-speed output correctness check)
- -40°C to +125°C Operating temperature range
- 28-lead, wide-body, finer pitch SOIC_W_FP package with 8.3mm creepage and clearance or 6mm x 6mm LFCSP package with 1.27mm creepage and clearance
Applications
- Isolated video and imaging data
- Analog front-end isolation
- Data plane isolation
- Isolated high-speed clock and data links
- Multi-gigabit serialization/deserialization (SERDES)
- Board-to-board optical replacement (for example, short-reach fiber)
Block Diagrams
Evaluation Board
Analog Devices Inc. EVAL-ADN4624EB1Z Evaluation Board
Used to evaluate the ADN4624 low voltage differential signaling (LVDS) isolator.
Additional Resources
Easily Calculate Sampling Clock Jitter for Isolated, Precision High-Speed DAQs
Jitter in the signal (or clock) controlling the S&H switch in an ADC impacts the SNR performance of precision, high-speed DAQ signal chains. Understanding the error sources that contribute to the overall jitter is important when selecting components.
Videos
Publicado: 2021-06-22
| Actualizado: 2022-12-04